View S6A0079X_356036.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
INTRODUCTION
S6A0079 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 2, or 4 lines with 5 x 8 dots format.
FUNCTIONS
-- -- -- -- -- --
Character type dot matrix LCD driver & controller Internal driver: 34 common and 120 segment signal output Easy interface with 4-bit or 8-bit MPU 5 x 8 dots matrix possible Voltage converter for LCD drive voltage: 13V max (2 times/3 times) Automatic power on reset
FEATURES
--
Internal memory - Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot) - Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot) - Icon RAM (CGRAM): 16 x 8 bits (80 icons max.) - Display Data RAM (DDRAM): 96 x 8 bits (96 characters max.) Low power operation - Power supply voltage range: 2.7 to 5.5V (V DD) - LCD Drive voltage range: 3.0 to 13.0V (V DD - V5) CMOS process Duty cycle: 1/33 Internal oscillator with an external resistor Bare chip available
--
-- -- -- --
PROGRAMMABLE DUTY CYCLES 5-Dot Font Width Display Line Numbers 2 4 1/33 1/33 Duty Ratio Single-chip Operation Displayable Characters 2-line of 48 characters 4-line of 24 characters Possible Icons 80 80
1
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
TEST1 OSC1OSC2
Power on Reset (POR) RESET TEST2 RS E RW System Interface 4-bit 8-bit 8 Instruction Register (IR)
Oscillator Timing Generator
Instruction Decoder
7 COM034-bit Common COM33 Shift Driver Register
Address Counter 7 7
Display Data RAM (DDRAM) 96 x 8-bit
8 8 DB4-DB7 Input/ Output Buffer Busy Flag LCD Driver Voltage Selector Data Register (DR) 8 SEG1120-bit 120-bit SEG120 Segment Shift Latch Driver Register Circuit
DB3-DB1
DB0
7
8
8
Vci C1 C2 Voltage Converter
Character Generator RAM (CGRAM) 64 bytes 5
Character Generator Cursor and ROM Blink (CGROM) 9600 bits Controller 5
V1 - V5
V5OUT2 V5OUT3 Parallel/Serial Converter and Smooth Scroll Circuit
VDD
GND(V SS)
2
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
PAD CONFIGURATION
SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148
Y
(0, 0)
X
Chip size: 5340x 8740 PAD size: 100x 100 Unit :m
S6A0079
147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
VDD OSC2 OSC1 RESET TEST2 TEST1 VSS1 RS RW E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCI C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
3
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
Table 1. Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pad Name SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 Coordinate X -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 Y 3540 3415 3290 3165 3040 2915 2790 2665 2540 2415 2290 2165 2040 1915 1790 1665 1540 1425 1290 1165 1040 915 790 665 540 415 290 165 40 -84 -209 -334 Pad No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pad Name SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 VDD OSC2 OSC1 RESET TEST2 Coordinate X -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -1750 -1625 -1500 -1375 -1250 Y -459 -584 -709 -834 -959 -1084 -1209 -1334 -1459 -1584 -1822 -1947 -2072 -2197 -2322 -2447 -2572 -2697 -2822 -2947 -3072 -3197 -3322 -3447 -3572 -3697 -3822 -4119 -4119 -4119 -4119 -4119 Pad No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pad Name TEST1 VSSI RS RW E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vci C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 Coordinate X -1125 -1000 -875 -750 -625 -500 -375 -250 -125 0 125 250 375 500 625 750 875 1000 1125 1250 1375 1500 1625 1750 2504 2504 2504 2504 2504 2504 2504 2504 Y -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -4119 -3822 -3697 -3572 -3447 -3322 -3197 -3072 -2947
4
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
Table 1. Pad Location (Continued)
Pad No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Pad Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 Coordinate X 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 Y -2822 -2697 -2572 -2447 -2322 -2197 -2072 -1947 -1822 -1584 -1459 -1334 -1209 -1084 -959 -834 -709 -584 -459 -334 -209 -84 40 165 290 415 540 665 790 915 1040 1165 1290 Pad No. 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 Pad Name SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 Coordinate X 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2187 2062 1937 1812 1687 1562 1437 1312 1187 1062 937 812 687 562 437 Y 1415 1540 1665 1790 1915 2040 2165 2290 2415 2540 2665 2790 2915 3040 3165 3290 3415 3540 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 Pad No. 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 Pad Name SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 Coordinate X 312 187 62 -62 -187 -312 -437 -562 -687 -812 -937 -1062 -1187 -1312 -1437 -1562 -1687 -1812 -1937 -2062 -2187 Y 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119 4119
5
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
Table 2. Pad Description Pad (No) VDD (60) VSS1, VSS2 (66, 81) V1-V5 (88-84) Vci (78) Input Input/ Output - Name Power supply Description For logical circuit (+3V, +5V) 0V (GND) Bias voltage level for LCD driving Interface Power supply
Input voltage to the voltage converter to generate LCD drive voltage (Vci = 1.0 - 4.5V). Segment output Common output Oscillator Segment signal output for LCD drive Common signal output for LCD drive LCD LCD
SEG1-SEG120 (1-42, 106-183) COM0-COM33 (105-89, 43-59) OSC1, OSC2 (61, 62)
Output Output Input (OSC1), Output (OSC2) Input
When use internal oscillator, connect External external Rf resistor. resistor/oscillator If external clock is used, connect it to OSC1. (OSC1) To use the voltage converter (2 times/3 times), these pins must be connected to the external capacitance. Initialized to low When TEST1 = "High", Test mode When TEST1 = "Low", Normal operation mode This pin must be set to VSS The value of Vci is converted two times. To use three times converter, the same capacitance as that of C1-C2 should be connected here. The value of Vci is converted three times. External capacitance - -
C1,C2 (80, 79) RESET (63) TEST1 (65)
External capacitance input Reset pin Test pin
Input Input
V5OUT2 (82)
Output
Two times converter output Three times converter output
V5 capacitance
V5OUT3 (83)
V5
TEST2 (64)
Input
Test pin
When TEST2 = "High" : Normal mode When TEST2 = "Low": Test mode This pin must be set to VDD Register selection input In RS = "High", Data register is selected. In RS = "Low", Instruction register is selected.
-
RS (67)
Input
Register select
MPU
6
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
Table 2. Pad Description (Continued) Pad (No) RW (68) Input/ Output Input Name Read/write Description Read/write selection input. In RW= "High", read operation. When RW = "Low", write operation. Read/write enable signal. Interface MPU
E (69)
Input
Read/write enable Data bus 0-7
MPU
DB0-DB3 (70-73) DB4-DB7 (74-77)
Input Output
In 8-bit bus mode, used as low order bidirectional data bus. During 4-bit bus mode, open these pins. In 8-bit bus mode, used as high order bidirectional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 used for busy flag output.
MPU
MPU
7
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE This chip has all two kinds interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode. RS 0 0 1 1 R/W 0 1 0 1 Operation Instruction write operation (MPU writes instruction code into IR) Read busy flag (DB7) and address counter (DB0 - DB6) Data write operation (MPU writes data into DR) Data read operation (MPU reads data from DR)
BUSY FLAG (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not high.
8
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
DISPLAY DATA RAM (DDRAM) DDRAM stores display data of maximum 96 x 8 bits (96 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSB AC6 AC5 AC4 AC3 AC2 AC1
LSB AC0
Figure 1. DDRAM Address 5-dot 2-line Display In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-2FH, 40H-6FH. (refer to Figure 2)
Display Position 12345 COM1 00 01 02 03 04 COM8 COM17 40 41 42 43 44 COM24 SEG1 20 21 22 23 24 13 14 15 16 17 44 45 46 47 48 COM9 2B 2C 2D 2E 2F COM16 COM25 53 54 55 56 57 58 59 5A 5B 5C .... 6B 6C 6D 6E 6F COM32 SEG120 SEG1 SEG120 DDRAM Address .... S6A0079 20 21 22 23 24 14 15 16 17 18 54 55 56 57 58 25 26 27 28 29 19 1A 1B 1C 1D 59 5A 5B 5C 5D 44 45 46 47 48 COM9 2C 2D 2E 2F 00 COM16 COM25 6C 6D 6E 6F 40 COM32 25 26 27 28 29 18 19 1A 1B 1C
.... ....
S6A0079 12345 COM1 01 02 03 04 05 COM8 COM17 41 42 43 44 45 COM24
.... ....
.... ....
(After Shift Left) 12345 COM1 2F 00 01 02 03 COM8 COM17 6F 40 41 42 43 COM24 20 21 22 23 24 12 13 14 15 16 52 53 54 55 56 25 26 27 28 29 17 18 19 1A 1B 57 58 59 5A 5B 44 45 46 47 48 COM9 2A 2B 2C 2D 2E COM16 COM25 6A 6B 6C 6D 6E COM32
.... ....
.... ....
(After Shift Right)
Figure 2. 2-line X 48ch. Display (5-dot Font Width)
9
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 4-line Display In case of 4-line display with 5 -dot font, the address range of DDRAM is 00H-17H, 20H-37H, 40H-57H, 60H-77H. (refer to Figure 3)
Display Position COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 1 2 3 4 5 .... .... .... .... 20 21 22 23 24 13 14 15 16 17 33 34 35 36 37 53 54 55 56 57 73 74 75 76 77 SEG120
00 01 02 03 04 20 21 22 23 24 40 41 42 43 44 60 61 62 63 64 SEG1
DDRAM Address S6A0079
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
12345 01 02 03 04 05 21 22 23 24 25 41 42 43 44 45 61 62 63 64 65
.... .... .... ....
20 21 22 23 24 14 15 16 17 00 34 35 36 37 20 54 55 56 57 40 74 75 76 77 60
(After Shift Left) 12345 17 00 01 02 03 37 20 21 22 23 57 40 41 42 43 77 60 61 62 63 20 21 22 23 24 12 13 14 15 16 32 33 34 35 36 52 53 54 55 56 72 73 74 75 76
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
.... .... .... ....
(After Shift Right)
Figure 3. 4-line X 24ch. Display (5-dot Font Width)
10
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
TIMING GENERATION CIRCUIT Timing generation circuit generates clock signals for the internal operations. ADDRESS COUNTER (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 - DB6. CURSOR/BLINK CONTROL CIRCUIT It controls cursor/blink ON/OFF and black/white inversion at cursor position. LCD DRIVER CIRCUIT LCD Driver circuit has 34 common and 120 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 120-bit segment latch serially, which is stored to 120-bit shift latch. When each common is selected by 34-bit common register, segment data also output through segment driver from 120-bit segment latch. In case of 2-line or 4-line mode, COM0-COM33 have 1/33 duty ratio. COM0 (COM33) makes the data of CGRAM (Icon RAM) enable to display icons.
11
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGROM (CHARACTER GENERATOR ROM) CGROM has 5 X 8 dots 240 characters pattern. CGRAM (Character Generator RAM) 5 x 8 Dot Character Pattern By writing font data to CGRAM, user defined character can be used. (refer to Table 4) pattern 7 and pattern 8 to CGRAM can be used in common by CGRAM and IconRAM. But CGRAM and IconRAM is used exclusively to pattern 7 or pattern 8 of CGRAM. CGRAM has up to 5 X 8-dot 6 - 8 characters. Table 4. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character Code (DDRAM data) CGRAM Address CGRAM Data D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0000x 000000000x x x 01110 001 10001 010 10001 . . . 011 11111 . . . . . . 100 10001 . . . 101 10001 . . . 110 10001 1 . . 0 0 0 0 x 1 1 0 1 . . 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 . . 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x x 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 0 . . 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 . . Pattern 7 Pattern Number Pattern 1
. . . . .
. . . . .
. . . . .
0
0
0
0
x
1
1
1
1
1
1
x
x
x
Pattern 8
. . . . .
. . . . .
. . . . .
12
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
CGRAM (ICON RAM) CGRAM (Icon RAM) has segment control data and segment pattern data. COM0(COM33) makes the data of CGRAM (Icon RAM) enable to display icons. Its lower 5-bit are pattern data. (refer to Table 5 and Figure 4) Table 5. Relationship Between CGRAM (Icon RAM) Address and Display Pattern
CGRAM Address CGRAM Data Display Pattern 5-Dot Font Width A5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 S76 S71 S66 S61 S56 S51 S46 S41 S36 S31 S26 S21 S16 S11 S6 S1 D3 S77 S72 S67 S62 S57 S52 S47 S42 S37 S32 S27 S22 S17 S12 S7 S2 D2 S78 S73 S68 S63 S58 S53 S48 S43 S38 S33 S28 S23 S18 S13 S8 S3 D1 S79 S74 S69 S64 S59 S54 S49 S44 S39 S34 S29 S24 S19 S14 S9 S4 D0 S80 S75 S70 S65 S60 S55 S50 S45 S40 S35 S30 S25 S20 S15 S10 S5 CGRAM pattern 8 CGRAM pattern 7
NOTES: 1. S1 - S80: Icon pattern ON/OFF in 5-dot font width. 2. "X": Don't care
13
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S1 S2 S3 S4 S5
S76S77S78S79S80
S111 S112 S113 S114 S115
S116 S117 S118 S119 S120
SEG1
SEG2
SEG3
SEG4
SEG5
SEG76
SEG77
SEG78
SEG79
SEG80
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
...
...
Figure 4. Relationship between CGRAM (Icon RAM) and Segment Display
14
SEG120
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
INSTRUCTION DESCRIPTION
OUTLINE To overcome the speed difference between internal clock of S6A0079 and MPU clock, S6A0079 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 6) Instruction can be divided largely four kinds, -- -- -- -- S6A0079 function set instructions (set display methods, set data length, etc.) Address set instructions to internal RAM Data transfer instructions with internal RAM Others
The address of internal RAM is automatically increased or decreased by 1.
NOTE: During internal operation, Busy Flag (DB7) is read High. Busy Flag check must precede the next instruction. When you make a MPU program with checking the Busy Flag (DB7), it must be necessary 1/2 fosc for executing the next instruction by falling E signal after the Busy Flag (DB7) goes to "Low".
15
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION Table 6. Instruction Set
Instruction RS Instruction Code R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 Description Execution Time (fosc = 270kHz)
Clear display Return home
0
Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction. I/D = "1": increment, I/D = "0": decrement and display shift enable bit. S = "1": make entire display shift of all lines during DDRAM write. S = "0": display shift disable Set display/cursor/blink on/off D = "1": display on, D = "0": display off, C = "1": cursor on, C = "0": cursor off, B = "1": blink on, B = "0": blink off. Cursor or display shift. S/C = "1": display shift, S/C = "0": cursor shift, R/L = "1": shift to right, R/L = "0": shift to left. Set interface data length (DL = "1": 8-bit, DL = "0": 4-bit), numbers of display line when (N = "1": 4-line, N = "0": 2-line).
1.53ms
0
0
0
0
0
0
0
0
1
X
1.53ms
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
39s
Display on/off control
0
0
0
0
0
0
1
D
C
B
39s
Cursor or display shift
0
0
0
0
0
1
S/C
R/L
X
X
39s
Function set
0
0
0
0
1
DL
N
X
X
X
39s
Set CGRAM address Set DDRAM address
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.
39s
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.
39s
16
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
Table 6. Instruction Set (Continued)
Instruction RS Read busy flag and address 0 Instruction Code R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = "1": busy state, BF = "0": ready state. D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Write data into internal RAM (DDRAM/CGRAM ). Read data from internal RAM (DDRAM/CGRAM ). Description Execution Time (fosc = 270kHz) 0s
Write data Read data
1 1
0 1
D7 D7
43s 43s
NOTES: 1. When an MPU program with busy flag (DB7) checking is made, 1/2 fosc is necessary for executing the next instruction by the "E" signal after the busy flag (DB7) goes to "Low". 2. "X": Don't care.
17
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. Entry mode is set to increment mode (I/D = "1") Return Home RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Set the moving direction of cursor and display. I/D: Increment/decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. - CGRAM operates the same as DDRAM, when read from or write to CGRAM.
When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0")or to the left (I/D = "1") but it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or CGRAM read/write operation, shift of entire display is not performed.
18
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1bit register. D: Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off.
C:
B:
Cursor or Display Shift RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 DB0 -
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after 48th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 24th digit of the current line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed.
Table 7. Shift Patterns According to S/C and R/L Bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, address counter is decreased by 1 Shift cursor to the right, address counter is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
19
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
Function Set RS 0 DL: R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 X DB1 X DB0 X
Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data by two times. Display line number control bit When N = "Low", it means 2-line display mode. When N = "High", 4-line display mode is set.
N:
Set CGRAM Address RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set DDRAM Address RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 2-line display mode (N = 0) DDRAM address in the 1st line is from "00H" to "2FH", and DDRAM address in the 2nd line is from "40H to 6FH". In 4-line display mode (N = 1), DDRAM address is from "00H to "17H" in the 1st line, from "20H" to "37H" in the 2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line. Read Busy Flag & Address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0079 is in internal operation or not. If the resultant BF is high, the internal operation is in progress and you have to wait until BF to be low, which by then the next instruction can be performed. In this instruction you can read the value of address counter.
20
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
Write Data to RAM RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM is set by the previous address set instruction : DDRAM address set, CGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. Read Data From RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, as the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, the correct RAM data can be from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, AC is increased/decreased by 1 as in read operation after this. In this time, AC indicates the next address position, but you can read only the previous data can only be read by read instruction.
21
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTERFACE WITH MPU
S6A0079 can transfer data in bus mode (4-bit or 8-bit) with MPU. Hence, both types of 4 or 8-bit MPU can be used. In case of 4-bit bus mode, data transfer is performed by twice to transfer 1 byte data.
--
When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by twice. busy flag outputs "High" after the second transfer is ended. When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7.
--
22
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
INTERFACE WITH MPU IN BUS MODE Interface with 8-bit MPU If 8-bit MPU is used, S6A0079 can connect directly with that. In this case, port E, RS, R/W and DB0 to DB7 need to interface each other. Example of timing sequence is shown below.
RS R/W E Internal Signal DB7
Data Internal Operation No Busy
Busy
Busy
Data
Instruction
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction
Figure 5. Example of 8-bit Bus Mode Timing Sequence
Interface with 4-bit MPU If 4-bit MPU is used, S6A0079 can connect directly with this. In this case, port E, RS, R/W and DB4 to DB7 need to interface each other. The transfer is performed by twice. Example of timing sequence is shown below.
RS R/W E Internal Signal DB7
D7 D3 Internal Operation No Busy
Busy
AC3
D7
D3
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Figure 6. Example of 4-bit Bus Mode Timing Sequence
23
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
APPLICATION INFORMATION ACCORDING TO LCD PANEL
LCD Panel: 48 Character x 2-line Format
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG118 SEG119 SEG120 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
S6A0079
24
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
LCD Panel: 24 Character x 4-line Format
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG118 SEG119 SEG120
S6A0079
25
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INITIALIZING
INITIALIZING BY INTERNAL RESET CIRCUIT When the power is turned on, S6A0079 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High" (busy state) to the end of initialization. Display Clear Instruction Write "20H" to all DDRAM Set Functions Instruction DL = 1: 8-bit bus mode N = 0: 2-line display mode Control Display ON/OFF Instruction D = 0: Display OFF C = 0: Cursor OFF B = 0: Blink OFF Set Entry Mode Instruction I/D = 1: Increment by 1 S = 0: No entire display shift INITIALIZING BY HARDWARE RESET INPUT When RESET pin = "Low", S6A0079 can be initialized like the case of power on reset. During the power on reset operation, this pin is ignored.
26
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
INITIALIZING BY INSTRUCTION
8-BIT INTERFACE MODE
Power On
Wait for more than 20ms after V DD rises to 4.5 V. Wait for more than 30ms after V DD rises to 2.7 V. (DL = "1") Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(1) DB3 N DB2 x DB1 x DB0
Condition: fosc = 270kHz
0 DL 1 0
4-bit interface 8-bit interface 1-line mode 2-bit interface
x
N 1
Wait for more than 39 s 0 D Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 C B B 1 Blink on 1 0 Wait for more than 39 s Cursor on Blink off 1 0 Display on Cursor off Display off
Clear Display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Wait for more than 1.53 sms 0 Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 0 S S 1 Initialization End Entire shift on Entire shift off I/D 1 Increment mode Decrement mode
27
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
4-BIT INTERFACE MODE
Power On
Wait for more than 20ms after V DD rises to 4.5 V. Wait for more than 30ms after V DD rises to 2.7 V. Condition: fosc = 270kHz (DL = "0") Function Set DL RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(0) DB3 x DB2 x DB1 x DB0 x N 1 Wait for more than 39 s 2-line mode 1 0 8-bit interface 1-line mode 0 4-bit interface
Function Set RS 0 0 R/W 0 0 DB7 0 N DB6 0 x DB5 1 x DB4 0 x DB3 x x DB2 x x DB1 x x DB0 x x
Wait for more than 39 s D
0 1
Display off Display on Cursor off Cursor on Blink off Blink on
Display ON/OFF Control 0 RS 0 0 R/W 0 0 DB7 0 1 DB6 0 D DB5 0 C DB4 0 B DB3 x x DB2 x x DB1 x x DB0 x 0 x B 1 Wait for more than 39 s C 1
Display Clear RS 0 0 R/W 0 0 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 1 DB3 x x DB2 x x DB1 x x DB0 x x
Wait for more than 1.53 ms 0 I/D DB3 x x DB2 x x DB1 x x DB0 x x S 1 Entire shift on 1 0 Increment mode Entire shift off Decrement mode
Entry Mode Set RS 0 0 R/W 0 0 DB7 0 0 DB6 0 1 DB5 0 I/D DB4 0 S
Initialization End
28
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
FRAME FREQUENCY
1/33 DUTY CYCLE
1-line selection period 1 VDD V1 COM1 V4 V5 1 Frame 1 Frame .. 2 3 4 ... 32 33 1 2 3 ... 32 33
1-line selection period Frame frequency
NOTE: fOSC = 270kHz (1 clock = 3.7s)
120 clocks 68.2Hz
29
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
POWER SUPPLY FOR DRIVING LCD PANEL
WHEN AN EXTERNAL POWER SUPPLY IS USED
VDD
R R R0 R R
VDD V1 V2 V3 V4 V5
VEE
WHEN AN INTERNAL BOOSTER IS USED
Boosting Twice VDD + 1F + Vci VDD GND V1 C1 V2 C2 V3 V5OUT2 V4 V5OUT3 V5 Can be detached if not using power down mode R R R0 R R VDD + 1F + Vci VDD GND V1 C1 V2 C2 V3 V5OUT2 V4 V5OUT3 V5 Can be detached if not using power down mode R R R0 R R Boosting Three Times
1F + 1F +
1F +
NOTES: 1. Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage. Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three times. 2. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice. 2. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (refer to Table 8)
30
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
Table 8. Duty Ratio and Power Supply for LCD Driving Item Number of lines Duty ratio Bias Divided resistance R R0 Data 2 or 4 1/33 1/6.7 R 2.7R
MAXIMUM ABSOLUTE RATE
Characteristic Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature
NOTE:
Symbol VDD VLCD VIN TOPR TSTG
Value -0.3 to +7.0 VDD -15.0 to VDD +0.3 -0.3 to VDD +0.3 -30 to +85 -55 to +125
Unit V V V C C
Voltage greater than above may damage to the circuit (VDD V1 V2 V3 V4 V5)
31
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (V DD = 2.7V to 5.5V, TA = -30 to +85C) Characteristic Operating voltage Supply current Symbol VDD IDD Condition - Internal oscillation or external clock. (V DD = 3.0V, fOSC = 270kHz) - VDD = 2.7 - 3.0 VDD = 3.0 - 5.5 Input voltage (2) (OSC1) Output voltage (1) (DB0 - DB7) Output voltage (2) (except DB0 - DB7) Voltage drop VIH2 VIL2 VOH1 VOL1 VOH2 VOL1 VdCOM VdSEG Input leakage current Low input current Internal clock (external Rf) External clock IIL IIN fOSC fEC duty tr, tf Voltage converter OUT2 (Vci = 4.5V) Voltage converter OUT3 (Vci = 2.7V) Voltage converter input LCD driving voltage VOUT2 VOUT3 Vci VLCD VDD-V5 TA = 25C, C = 1F, IOUT = 0.25mA, fOSC = 270kHz - 1/6.7 bias -4.3 1.0 3.0 -5.1 - - - 4.5 13.0 V VIN = 0V - VDD VIN = 0V, VDD = 3V (pull up) Rf = 91k 2% (V DD = 5V) - IOH = -0.1mA IOL = 0.1mA IO = -40A IO = 40A IO = 0.1mA - - Min 2.7 - Typ - 0.15 Max 5.5 0.3 Unit V mA
Input voltage (1) (Except OSC1)
VIH1 VIL1
0.7V DD -0.3 -0.3 0.7V DD - 0.75V DD - 0.8V DD - - -1 -10 190 125 45 - -3.0
- - - - - - - - - - - - -50 270 270 50 - -4.2
VDD 0.2V DD 0.6 VDD 0.2V DD - 0.2V DD - 0.2V DD 1 1 1 -120 350 410 55 0.2 -
-
V
V
V
V
A
kHz kHz % s V
32
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
AC CHARACTERISTICS (V DD = 4.5 to 5.5V, TA = -30 to + 85C) Mode Write mode (1) (refer to Figure 7) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data setup time Data hold time Read mode (2) (refer to Figure 8) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data output delay time Data hold time Item Symbol tC tr, tf tW tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH Min 500 - 230 40 10 60 10 500 - 230 40 10 - 5 Typ - - - - - - - - - - - - - - Max - 20 - - - - - - 20 - - - 160 - ns Unit ns
(V DD = 2.7 to 4.5V, TA = -30 to + 85C) Mode Write mode (3) (refer to Figure 7) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data setup time Data hold time Read mode (4) (refer to Figure 8) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data output delay time Data hold time Item Symbol tc, tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH Min 1000 - 450 60 20 195 10 1000 - 450 60 20 - 5 Typ - - - - - - - - - - - - - - Max - 25 - - - - - - 25 - - - 360 - ns Unit ns
33
S6A0079
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
34
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0079
RS
VIH1 VIL1 tSU1 VIL1 tW
t H1 VIL1 tH1 tF VIH1 VIL1 tSU2 Valid Data tC
R/W
E tR DB0 - DB7
VIH1 VIL1 VIH1 VIL1
VIL1 tH2 VIH1 VIL1
Figure 7. Write Mode
RS
VIH1 VIL1 tSU VIH1 tW
tH VIH1 tH tF VIH1 VIL1 tD VOH1 VOL1 tDH Valid Data tC VOH1 VOL1
R/W
E tR DB0 - DB7
VIH1 VIL1
VIL1
Figure 8. Read Mode
RESET TIMING (V DD = 2.7 to 5.5V, TA = -30 to +85C) Item Reset low level width (refer to Figure 9) Symbol tRES Min 10 Typ - Max - Unit ms
tRES RESET VIL1 VIL1
Figure 9. Reset Timing Diagram
35

▲Up To Search▲

Price & Availability of S6A0079X

	To Download S6A0079X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .